added v2.0
This commit is contained in:
Michael Schröder
34
03_Sequential_Logic/05_RAM3840/Include.v
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34
03_Sequential_Logic/05_RAM3840/Include.v
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`include "../../01_Boolean_Logic/Nand.v"
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`include "../../01_Boolean_Logic/Not.v"
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`include "../../01_Boolean_Logic/Buffer.v"
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`include "../../01_Boolean_Logic/And.v"
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`include "../../01_Boolean_Logic/Or.v"
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`include "../../01_Boolean_Logic/Xor.v"
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`include "../../01_Boolean_Logic/Mux.v"
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`include "../../01_Boolean_Logic/DMux.v"
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`include "../../01_Boolean_Logic/Not16.v"
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`include "../../01_Boolean_Logic/Buffer16.v"
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`include "../../01_Boolean_Logic/And16.v"
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`include "../../01_Boolean_Logic/Or16.v"
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`include "../../01_Boolean_Logic/Mux16.v"
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`include "../../01_Boolean_Logic/Or8Way.v"
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`include "../../01_Boolean_Logic/Mux4Way16.v"
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`include "../../01_Boolean_Logic/Mux8Way16.v"
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`include "../../01_Boolean_Logic/DMux4Way.v"
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`include "../../01_Boolean_Logic/DMux8Way.v"
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`include "../../02_Boolean_Arithmetic/HalfAdder.v"
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`include "../../02_Boolean_Arithmetic/FullAdder.v"
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`include "../../02_Boolean_Arithmetic/Add16.v"
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`include "../../02_Boolean_Arithmetic/Inc16.v"
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`include "../../02_Boolean_Arithmetic/ALU.v"
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`include "../../03_Sequential_Logic/DFF.v"
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`include "../../03_Sequential_Logic/Bit.v"
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`include "../../03_Sequential_Logic/Register.v"
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`include "../../03_Sequential_Logic/PC.v"
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`include "../../03_Sequential_Logic/RAM256.v"
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`include "../../03_Sequential_Logic/RAM512.v"
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`include "../../03_Sequential_Logic/RAM3840.v"
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`include "../../03_Sequential_Logic/BitShift8L.v"
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`include "../../03_Sequential_Logic/BitShift9R.v"
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40
03_Sequential_Logic/05_RAM3840/PC_tb.gtkw
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40
03_Sequential_Logic/05_RAM3840/PC_tb.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Thu Dec 22 17:44:56 2022
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[*]
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[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd"
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[dumpfile_mtime] "Thu Dec 22 17:44:20 2022"
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[dumpfile_size] 627445
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[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw"
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[timestart] 0
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[size] 1920 963
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[pos] -1 -1
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*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 281
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[signals_width] 160
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[sst_expanded] 1
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[sst_vpaned_height] 258
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@28
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PC_tb.clk
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@200
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-IN
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@22
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PC_tb.in[15:0]
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@28
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PC_tb.load
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PC_tb.inc
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PC_tb.reset
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@200
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-OUT
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@22
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PC_tb.out[15:0]
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@200
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-CMP
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@22
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PC_tb.out_cmp[15:0]
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@200
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-Test
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@29
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PC_tb.fail
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[pattern_trace] 1
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[pattern_trace] 0
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40
03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw
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40
03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Sat Dec 31 11:27:32 2022
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[*]
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[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/05_RAM3840/RAM3840_tb.vcd"
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[dumpfile_mtime] "Sat Dec 31 11:26:49 2022"
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[dumpfile_size] 19516827
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[savefile] "/home/micha/gitlab/nand2tetris-fpga/03_Sequential_Logic/05_RAM3840/RAM3840_tb.gtkw"
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[timestart] 0
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[size] 1616 559
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[pos] -1 -1
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*-11.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 281
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[signals_width] 160
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[sst_expanded] 1
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[sst_vpaned_height] 117
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@28
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RAM3840_tb.clk
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@200
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-IN
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@22
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RAM3840_tb.address[11:0]
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@29
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RAM3840_tb.load
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@22
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RAM3840_tb.in[15:0]
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@200
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-OUT
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@22
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RAM3840_tb.out[15:0]
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@200
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-CMP
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@22
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RAM3840_tb.out_cmp[15:0]
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@200
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-Test
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@28
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RAM3840_tb.fail
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[pattern_trace] 1
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[pattern_trace] 0
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60
03_Sequential_Logic/05_RAM3840/RAM3840_tb.v
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60
03_Sequential_Logic/05_RAM3840/RAM3840_tb.v
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`default_nettype none
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module RAM3840_tb();
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// IN,OUT
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reg clk=1;
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reg [15:0] in;
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reg [11:0] address;
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reg load;
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wire [15:0] out;
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// Part
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RAM3840 RAM3840(
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.clk(clk),
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.address(address),
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.in(in),
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.load(load),
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.out(out)
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);
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// Simulate
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always #1 clk=~clk;
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always @(posedge clk) begin
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in <= $random;
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address <= (n<3840)?n:n-3840;
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load <= (n<3840);
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end
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// Compare
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reg [15:0] regRAM [0:3839];
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always @(posedge clk)
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if (load) regRAM[address[11:0]] <= in;
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wire[15:0] out_cmp = regRAM[address[11:0]];
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reg fail = 0;
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reg [15:0] n = 0;
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task check;
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#1
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if (out != out_cmp)
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begin
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$display("FAIL: clk=%1b, address=%12b, in=%16b, load=%1b, out=%16b",clk,address,in,load,out);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("RAM3840_tb.vcd");
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$dumpvars(0, RAM3840_tb);
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$display("------------------------");
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$display("Testbench: RAM3840");
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for (n=0; n<2*3840;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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3
03_Sequential_Logic/05_RAM3840/apio.ini
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3
03_Sequential_Logic/05_RAM3840/apio.ini
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@@ -0,0 +1,3 @@
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[env]
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board = iCE40-HX1K-EVB
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