added v2.0

03_Sequential_Logic/03_PC/Include.v

@@ -0,0 +1,31 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
+`include "../../03_Sequential_Logic/DFF.v"
+`include "../../03_Sequential_Logic/Bit.v"
+`include "../../03_Sequential_Logic/Register.v"
+`include "../../03_Sequential_Logic/PC.v"
+`include "../../03_Sequential_Logic/BitShift8L.v"
+`include "../../03_Sequential_Logic/BitShift9R.v"

03_Sequential_Logic/03_PC/PC_tb.gtkw

@@ -0,0 +1,40 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:44:56 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:44:20 2022"
+[dumpfile_size] 627445
+[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/03_PC/PC_tb.gtkw"
+[timestart] 0
+[size] 1920 963
+[pos] -1 -1
+*-3.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 258
+@28
+PC_tb.clk
+@200
+-IN
+@22
+PC_tb.in[15:0]
+@28
+PC_tb.load
+PC_tb.inc
+PC_tb.reset
+@200
+-OUT
+@22
+PC_tb.out[15:0]
+@200
+-CMP
+@22
+PC_tb.out_cmp[15:0]
+@200
+-Test
+@29
+PC_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

03_Sequential_Logic/03_PC/PC_tb.v

@@ -0,0 +1,60 @@
+`default_nettype none
+module PC_tb();
+
+	// IN,OUT
+	reg clk=1;
+	reg [15:0] in;
+	reg load,inc,reset;
+	wire [15:0] out;
+
+	// Part
+	PC PC(
+		.clk(clk),
+		.in(in),
+		.load(load),
+		.inc(inc),
+		.reset(reset),
+		.out(out)
+	);
+
+	// Simulate
+	always #1 clk=~clk;
+	always @(posedge clk) begin
+		in <= $random;	
+		reset <= (n==10) || (n==24) || (n==44);
+		inc <= $random;
+		load <= $random;
+	end
+
+	// Compare
+	reg [15:0] out_cmp;
+	always @(posedge clk)
+		out_cmp <= (reset?0:(load?in:(inc?out+1:out)));	
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: clk=%1b, in=%16b, load=%1b, inc=%1b, reset=%1b, out=%16b",clk,in,load,inc,reset,out);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("PC_tb.vcd");
+  		$dumpvars(0, PC_tb);
+		
+		$display("------------------------");
+		$display("Testbench: PC");
+
+		for (n=0; n<1000;n=n+1) 
+			check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

03_Sequential_Logic/03_PC/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+