added v2.0

03_Sequential_Logic/01_Bit/Bit_tb.gtkw

@@ -0,0 +1,38 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 17:43:28 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/01_Bit/Bit_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 17:42:58 2022"
+[dumpfile_size] 29689
+[savefile] "/home/micha/gitlab/nand2tetris/03_Sequential_Logic/01_Bit/Bit_tb.gtkw"
+[timestart] 0
+[size] 1709 600
+[pos] -1 -1
+*-2.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] Bit_tb.
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@28
+Bit_tb.clk
+@200
+-IN
+@28
+Bit_tb.in
+Bit_tb.load
+@200
+-OUT
+@28
+Bit_tb.out
+@200
+-CMP
+@28
+Bit_tb.out_cmp
+@201
+-Test
+@28
+Bit_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

03_Sequential_Logic/01_Bit/Bit_tb.v

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+`default_nettype none
+module Bit_tb();
+
+	// IN,OUT
+	reg clk = 1;
+	reg in,load;
+	wire out;
+
+	// Part
+	Bit BIT(
+		.clk(clk),
+		.in(in),
+		.load(load),
+		.out(out)
+	);
+
+	// Compare
+	always #1 clk=~clk;
+	always @(posedge clk) begin
+		in <= $random;	
+		load <= $random;
+	end
+	reg out_cmp;
+	always @(posedge clk)
+		out_cmp <= (load?in:out);	
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: clk=%1b, in=%1b, load=%1b, out=%1b",clk,in,load,out);
+				fail=1;
+			end
+	endtask
+	  
+  	initial begin
+  		$dumpfile("Bit_tb.vcd");
+  		$dumpvars(0, Bit_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Bit");
+
+		for (n=0; n<1000;n=n+1) 
+			check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

03_Sequential_Logic/01_Bit/Include.v

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+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"
+`include "../../01_Boolean_Logic/Mux8Way16.v"
+`include "../../01_Boolean_Logic/DMux4Way.v"
+`include "../../01_Boolean_Logic/DMux8Way.v"
+
+`include "../../02_Boolean_Arithmetic/HalfAdder.v"
+`include "../../02_Boolean_Arithmetic/FullAdder.v"
+`include "../../02_Boolean_Arithmetic/Add16.v"
+`include "../../02_Boolean_Arithmetic/Inc16.v"
+`include "../../02_Boolean_Arithmetic/ALU.v"
+
+`include "../../03_Sequential_Logic/DFF.v"
+`include "../../03_Sequential_Logic/Bit.v"
+`include "../../03_Sequential_Logic/Register.v"
+`include "../../03_Sequential_Logic/PC.v"
+`include "../../03_Sequential_Logic/BitShift8L.v"
+`include "../../03_Sequential_Logic/BitShift9R.v"

03_Sequential_Logic/01_Bit/apio.ini

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+[env]
+board = iCE40-HX1K-EVB
+