added v2.0

This commit is contained in:
Michael Schröder
2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions

View File

@@ -0,0 +1,43 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 14:40:27 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/15_DMux4Way/DMux4Way_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 14:39:53 2022"
[dumpfile_size] 4551
[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/15_DMux4Way/DMux4Way_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*-1.619024 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 110
[sst_expanded] 1
[sst_vpaned_height] 258
@200
-IN
@28
DMux4Way_tb.in
DMux4Way_tb.sel[1:0]
@200
-OUT
@28
DMux4Way_tb.a
DMux4Way_tb.b
DMux4Way_tb.c
DMux4Way_tb.d
@200
-CMP
@28
DMux4Way_tb.a_cmp
@29
DMux4Way_tb.b_cmp
@28
DMux4Way_tb.c_cmp
DMux4Way_tb.d_cmp
@200
-Test
@28
DMux4Way_tb.fail
[pattern_trace] 1
[pattern_trace] 0

View File

@@ -0,0 +1,57 @@
`default_nettype none
module DMux4Way_tb();
// IN,OUT
reg in;
reg [1:0] sel;
wire a,b,c,d;
// Part
DMux4Way DMUX4WAY(
.in(in),
.sel(sel),
.a(a),
.b(b),
.c(c),
.d(d)
);
// Compare
wire a_cmp,b_cmp,c_cmp,d_cmp;
assign a_cmp = (sel==0)?in:0;
assign b_cmp = (sel==1)?in:0;
assign c_cmp = (sel==2)?in:0;
assign d_cmp = (sel==3)?in:0;
reg fail = 0;
task check;
#1
if ((a != a_cmp) || (b != b_cmp) || (c != c_cmp) || (d != d_cmp))
begin
$display("FAIL: in=%1b, sel=%1b, a=%1b, b=%1b, c=%1b, d=%1b",in,sel,a,b,c,d);
fail=1;
end
endtask
initial begin
$dumpfile("DMux4Way_tb.vcd");
$dumpvars(0, DMux4Way_tb);
$display("------------------------");
$display("Testbench: DMux4Way");
in=0;sel=0;check();
in=0;sel=1;check();
in=0;sel=2;check();
in=0;sel=3;check();
in=1;sel=0;check();
in=1;sel=1;check();
in=1;sel=2;check();
in=1;sel=3;check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

View File

@@ -0,0 +1,17 @@
`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"
`include "../../01_Boolean_Logic/DMux4Way.v"

View File

@@ -0,0 +1,3 @@
[env]
board = iCE40-HX1K-EVB