added v2.0

This commit is contained in:
Michael Schröder
2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions

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`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"
`include "../../01_Boolean_Logic/And16.v"
`include "../../01_Boolean_Logic/Or16.v"
`include "../../01_Boolean_Logic/Mux16.v"
`include "../../01_Boolean_Logic/Or8Way.v"
`include "../../01_Boolean_Logic/Mux4Way16.v"
`include "../../01_Boolean_Logic/Mux8Way16.v"

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[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 14:41:14 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 14:40:51 2022"
[dumpfile_size] 2373256
[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.gtkw"
[timestart] 0
[size] 1920 963
[pos] -1 -1
*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 259
@200
-IN
@22
Mux8Way16_tb.a[15:0]
Mux8Way16_tb.b[15:0]
Mux8Way16_tb.c[15:0]
Mux8Way16_tb.d[15:0]
Mux8Way16_tb.e[15:0]
Mux8Way16_tb.f[15:0]
Mux8Way16_tb.g[15:0]
Mux8Way16_tb.h[15:0]
@28
Mux8Way16_tb.sel[2:0]
@200
-OUT
@22
Mux8Way16_tb.out[15:0]
@200
-CMP
@22
Mux8Way16_tb.out_cmp[15:0]
@201
-Test
@28
Mux8Way16_tb.fail
[pattern_trace] 1
[pattern_trace] 0

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`default_nettype none
module Mux8Way16_tb();
// IN,OUT
reg [15:0] a,b,c,d,e,f,g,h;
reg [2:0] sel;
wire [15:0] out;
// PART
Mux8Way16 MUX8WAY16(
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.h(h),
.sel(sel),
.out(out)
);
// Compare
wire [15:0] out_cmp;
assign out_cmp = (sel[2]?(sel[1]? (sel[0]?h:g):(sel[0]?f:e)):
(sel[1]? (sel[0]?d:c):(sel[0]?b:a)));
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: a=%16b, b=%16b, c=%16b, d=%16b, e=%16b, f=%16b, g=%16b, h=%16b, sel=%3b, out=%16b",a,b,c,d,e,f,g,h,sel,out);
fail=1;
end
endtask
initial begin
$dumpfile("Mux8Way16_tb.vcd");
$dumpvars(0, Mux8Way16_tb);
$display("------------------------");
$display("Testbench: Mux8Way16");
for (n=0; n<100;n=n+1)
begin
a=$random;
b=$random;
c=$random;
d=$random;
e=$random;
f=$random;
g=$random;
h=$random;
sel=0;check();
sel=1;check();
sel=2;check();
sel=3;check();
sel=4;check();
sel=5;check();
sel=6;check();
sel=7;check();
end
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

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[env]
board = iCE40-HX1K-EVB