added v2.0
This commit is contained in:
16
01_Boolean_Logic/15_Mux8Way16/Include.v
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16
01_Boolean_Logic/15_Mux8Way16/Include.v
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`include "../../01_Boolean_Logic/Nand.v"
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`include "../../01_Boolean_Logic/Not.v"
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`include "../../01_Boolean_Logic/Buffer.v"
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`include "../../01_Boolean_Logic/And.v"
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`include "../../01_Boolean_Logic/Or.v"
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`include "../../01_Boolean_Logic/Xor.v"
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`include "../../01_Boolean_Logic/Mux.v"
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`include "../../01_Boolean_Logic/DMux.v"
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`include "../../01_Boolean_Logic/Not16.v"
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`include "../../01_Boolean_Logic/Buffer16.v"
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`include "../../01_Boolean_Logic/And16.v"
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`include "../../01_Boolean_Logic/Or16.v"
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`include "../../01_Boolean_Logic/Mux16.v"
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`include "../../01_Boolean_Logic/Or8Way.v"
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`include "../../01_Boolean_Logic/Mux4Way16.v"
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`include "../../01_Boolean_Logic/Mux8Way16.v"
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43
01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.gtkw
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43
01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Thu Dec 22 14:41:14 2022
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[*]
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[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.vcd"
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[dumpfile_mtime] "Thu Dec 22 14:40:51 2022"
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[dumpfile_size] 2373256
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[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/14_Mux8Way16/Mux8Way16_tb.gtkw"
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[timestart] 0
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[size] 1920 963
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[pos] -1 -1
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*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 281
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[signals_width] 160
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[sst_expanded] 1
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[sst_vpaned_height] 259
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@200
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-IN
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@22
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Mux8Way16_tb.a[15:0]
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Mux8Way16_tb.b[15:0]
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Mux8Way16_tb.c[15:0]
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Mux8Way16_tb.d[15:0]
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Mux8Way16_tb.e[15:0]
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Mux8Way16_tb.f[15:0]
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Mux8Way16_tb.g[15:0]
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Mux8Way16_tb.h[15:0]
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@28
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Mux8Way16_tb.sel[2:0]
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@200
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-OUT
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@22
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Mux8Way16_tb.out[15:0]
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@200
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-CMP
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@22
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Mux8Way16_tb.out_cmp[15:0]
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@201
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-Test
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@28
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Mux8Way16_tb.fail
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[pattern_trace] 1
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[pattern_trace] 0
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71
01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.v
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71
01_Boolean_Logic/15_Mux8Way16/Mux8Way16_tb.v
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`default_nettype none
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module Mux8Way16_tb();
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// IN,OUT
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reg [15:0] a,b,c,d,e,f,g,h;
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reg [2:0] sel;
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wire [15:0] out;
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// PART
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Mux8Way16 MUX8WAY16(
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.a(a),
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.b(b),
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.c(c),
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.d(d),
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.e(e),
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.f(f),
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.g(g),
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.h(h),
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.sel(sel),
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.out(out)
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);
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// Compare
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wire [15:0] out_cmp;
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assign out_cmp = (sel[2]?(sel[1]? (sel[0]?h:g):(sel[0]?f:e)):
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(sel[1]? (sel[0]?d:c):(sel[0]?b:a)));
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reg fail = 0;
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reg [15:0] n = 0;
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task check;
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#1
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if (out != out_cmp)
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begin
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$display("FAIL: a=%16b, b=%16b, c=%16b, d=%16b, e=%16b, f=%16b, g=%16b, h=%16b, sel=%3b, out=%16b",a,b,c,d,e,f,g,h,sel,out);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("Mux8Way16_tb.vcd");
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$dumpvars(0, Mux8Way16_tb);
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$display("------------------------");
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$display("Testbench: Mux8Way16");
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for (n=0; n<100;n=n+1)
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begin
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a=$random;
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b=$random;
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c=$random;
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d=$random;
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e=$random;
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f=$random;
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g=$random;
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h=$random;
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sel=0;check();
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sel=1;check();
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sel=2;check();
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sel=3;check();
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sel=4;check();
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sel=5;check();
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sel=6;check();
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sel=7;check();
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end
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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3
01_Boolean_Logic/15_Mux8Way16/apio.ini
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3
01_Boolean_Logic/15_Mux8Way16/apio.ini
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@@ -0,0 +1,3 @@
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[env]
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board = iCE40-HX1K-EVB
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