added v2.0

01_Boolean_Logic/14_Mux4Way16/Include.v

@@ -0,0 +1,15 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"
+`include "../../01_Boolean_Logic/Xor.v"
+`include "../../01_Boolean_Logic/Mux.v"
+`include "../../01_Boolean_Logic/DMux.v"
+`include "../../01_Boolean_Logic/Not16.v"
+`include "../../01_Boolean_Logic/Buffer16.v"
+`include "../../01_Boolean_Logic/And16.v"
+`include "../../01_Boolean_Logic/Or16.v"
+`include "../../01_Boolean_Logic/Mux16.v"
+`include "../../01_Boolean_Logic/Or8Way.v"
+`include "../../01_Boolean_Logic/Mux4Way16.v"

01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.gtkw

@@ -0,0 +1,40 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:42:01 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/13_Mux4Way16/Mux4Way16_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:41:40 2022"
+[dumpfile_size] 4764720
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/13_Mux4Way16/Mux4Way16_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*0.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] Mux4Way16_tb.
+[sst_width] 281
+[signals_width] 160
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@22
+Mux4Way16_tb.a[15:0]
+Mux4Way16_tb.b[15:0]
+Mux4Way16_tb.c[15:0]
+Mux4Way16_tb.d[15:0]
+@28
+Mux4Way16_tb.sel[1:0]
+@200
+-OUT
+@22
+Mux4Way16_tb.out[15:0]
+@200
+-CMP
+@22
+Mux4Way16_tb.out_cmp[15:0]
+@201
+-Test
+@28
+Mux4Way16_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/14_Mux4Way16/Mux4Way16_tb.v

@@ -0,0 +1,59 @@
+`default_nettype none
+module Mux4Way16_tb();
+
+	// IN,OUT
+	reg [15:0] a,b,c,d;
+	reg [1:0] sel;
+	wire [15:0] out;
+	
+	// Part
+	Mux4Way16 MUX4WAY16(
+		.a(a),
+		.b(b),
+		.c(c),
+		.d(d),
+		.sel(sel),
+		.out(out)
+	);
+
+	// Compare
+	wire [15:0] out_cmp;
+	assign out_cmp = (sel[1]? (sel[0]?d:c):(sel[0]?b:a));
+	
+	reg fail = 0;
+	reg [15:0] n = 0;
+	task check;
+		#1
+			if (out != out_cmp)
+			begin
+				$display("FAIL: a=%16b, b=%16b, c=%16b, d=%16b, sel=%2b, out=%16b",a,b,c,d,sel,out);
+				fail=1;
+			end
+	endtask
+	 
+	// Test 
+  	initial begin
+  		$dumpfile("Mux4Way16_tb.vcd");
+  		$dumpvars(0, Mux4Way16_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Mux4Way16");
+		
+		for (n=0; n<1000;n=n+1) 
+			begin
+				a=$random;
+				b=$random;
+				c=$random;
+				d=$random;
+				sel=0;check();
+				sel=1;check();
+				sel=2;check();
+				sel=3;check();
+			end
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/14_Mux4Way16/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = iCE40-HX1K-EVB
+