added v2.0

This commit is contained in:
Michael Schröder
2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions

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[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Wed Jan 4 11:28:38 2023
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris-fpga/01_Boolean_Logic/09_Buffer16/Buffer16_tb.vcd"
[dumpfile_mtime] "Wed Jan 4 11:27:59 2023"
[dumpfile_size] 3089054
[savefile] "/home/micha/gitlab/nand2tetris-fpga/01_Boolean_Logic/09_Buffer16/Buffer16_tb.gtkw"
[timestart] 0
[size] 1547 481
[pos] -1 -1
*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 160
[sst_expanded] 1
[sst_vpaned_height] 91
@200
-IN
@23
Buffer16_tb.in[15:0]
@200
-OUT
@22
Buffer16_tb.out[15:0]
@200
-CMP
@22
Buffer16_tb.out_cmp[15:0]
@200
-Test
@28
Buffer16_tb.fail
[pattern_trace] 1
[pattern_trace] 0

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`default_nettype none
module Buffer16_tb();
// IN,OUT
reg [15:0] in;
wire [15:0] out;
// Part
Buffer16 BUFFER16(
.in(in),
.out(out)
);
// Compare
wire [15:0] out_cmp;
assign out_cmp = in;
reg fail = 0;
reg [15:0] n = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: in=%16b, out=%16b",in,out);
fail=1;
end
endtask
// Test
initial begin
$dumpfile("Buffer16_tb.vcd");
$dumpvars(0, Buffer16_tb);
$display("------------------------");
$display("Testbench: Buffer16");
for (n=0; n<10000;n=n+1)
begin
in=$random;
check();
end
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

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`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"
`include "../../01_Boolean_Logic/DMux.v"
`include "../../01_Boolean_Logic/Not16.v"
`include "../../01_Boolean_Logic/Buffer16.v"

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[env]
board = iCE40-HX1K-EVB