added v2.0

This commit is contained in:
Michael Schröder
2023-01-11 11:13:09 +01:00
parent 2a5a64ca91
commit 971b323822
584 changed files with 159319 additions and 0 deletions

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`include "../../01_Boolean_Logic/Nand.v"
`include "../../01_Boolean_Logic/Not.v"
`include "../../01_Boolean_Logic/Buffer.v"
`include "../../01_Boolean_Logic/And.v"
`include "../../01_Boolean_Logic/Or.v"
`include "../../01_Boolean_Logic/Xor.v"
`include "../../01_Boolean_Logic/Mux.v"

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[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Dec 22 14:49:39 2022
[*]
[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.vcd"
[dumpfile_mtime] "Thu Dec 22 14:49:24 2022"
[dumpfile_size] 2362
[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.gtkw"
[timestart] 0
[size] 1000 600
[pos] -1 -1
*-1.619024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 281
[signals_width] 100
[sst_expanded] 1
[sst_vpaned_height] 132
@200
-IN
@28
Mux_tb.a
Mux_tb.b
Mux_tb.sel
@200
-OUT
@28
Mux_tb.out
@200
-CMP
@29
Mux_tb.out_cmp
@200
-Test
@28
Mux_tb.fail
[pattern_trace] 1
[pattern_trace] 0

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`default_nettype none
module Mux_tb();
// IN,OUT
reg a,b,sel;
wire out;
// Part
Mux MUX(
.a(a),
.b(b),
.sel(sel),
.out(out)
);
// Compare
wire out_cmp;
assign out_cmp = (sel?b:a);
reg fail = 0;
task check;
#1
if (out != out_cmp)
begin
$display("FAIL: a=%1b, b=%1b, sel=%1b, out=%1b",a,b,sel,out);
fail=1;
end
endtask
// Test
initial begin
$dumpfile("Mux_tb.vcd");
$dumpvars(0, Mux_tb);
$display("------------------------");
$display("Testbench: Mux");
a=0;b=0;sel=0;check();
a=0;b=0;sel=1;check();
a=0;b=1;sel=0;check();
a=0;b=1;sel=1;check();
a=1;b=0;sel=0;check();
a=1;b=0;sel=1;check();
a=1;b=1;sel=0;check();
a=1;b=1;sel=1;check();
if (fail==0) $display("passed");
$display("------------------------");
$finish;
end
endmodule

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[env]
board = iCE40-HX1K-EVB