added v2.0
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7
01_Boolean_Logic/06_Mux/Include.v
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7
01_Boolean_Logic/06_Mux/Include.v
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`include "../../01_Boolean_Logic/Nand.v"
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`include "../../01_Boolean_Logic/Not.v"
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`include "../../01_Boolean_Logic/Buffer.v"
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`include "../../01_Boolean_Logic/And.v"
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`include "../../01_Boolean_Logic/Or.v"
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`include "../../01_Boolean_Logic/Xor.v"
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`include "../../01_Boolean_Logic/Mux.v"
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36
01_Boolean_Logic/06_Mux/Mux_tb.gtkw
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36
01_Boolean_Logic/06_Mux/Mux_tb.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Thu Dec 22 14:49:39 2022
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[*]
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[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.vcd"
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[dumpfile_mtime] "Thu Dec 22 14:49:24 2022"
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[dumpfile_size] 2362
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[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/06_Mux/Mux_tb.gtkw"
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[timestart] 0
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[size] 1000 600
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[pos] -1 -1
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*-1.619024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 281
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[signals_width] 100
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[sst_expanded] 1
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[sst_vpaned_height] 132
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@200
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-IN
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@28
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Mux_tb.a
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Mux_tb.b
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Mux_tb.sel
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@200
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-OUT
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@28
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Mux_tb.out
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@200
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-CMP
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@29
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Mux_tb.out_cmp
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@200
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-Test
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@28
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Mux_tb.fail
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[pattern_trace] 1
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[pattern_trace] 0
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52
01_Boolean_Logic/06_Mux/Mux_tb.v
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52
01_Boolean_Logic/06_Mux/Mux_tb.v
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`default_nettype none
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module Mux_tb();
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// IN,OUT
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reg a,b,sel;
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wire out;
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// Part
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Mux MUX(
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.a(a),
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.b(b),
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.sel(sel),
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.out(out)
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);
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// Compare
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wire out_cmp;
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assign out_cmp = (sel?b:a);
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reg fail = 0;
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task check;
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#1
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if (out != out_cmp)
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begin
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$display("FAIL: a=%1b, b=%1b, sel=%1b, out=%1b",a,b,sel,out);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("Mux_tb.vcd");
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$dumpvars(0, Mux_tb);
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$display("------------------------");
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$display("Testbench: Mux");
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a=0;b=0;sel=0;check();
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a=0;b=0;sel=1;check();
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a=0;b=1;sel=0;check();
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a=0;b=1;sel=1;check();
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a=1;b=0;sel=0;check();
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a=1;b=0;sel=1;check();
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a=1;b=1;sel=0;check();
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a=1;b=1;sel=1;check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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3
01_Boolean_Logic/06_Mux/apio.ini
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3
01_Boolean_Logic/06_Mux/apio.ini
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[env]
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board = iCE40-HX1K-EVB
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