added v2.0

01_Boolean_Logic/04_Or/Include.v

@@ -0,0 +1,5 @@
+`include "../../01_Boolean_Logic/Nand.v"
+`include "../../01_Boolean_Logic/Not.v"
+`include "../../01_Boolean_Logic/Buffer.v"
+`include "../../01_Boolean_Logic/And.v"
+`include "../../01_Boolean_Logic/Or.v"

01_Boolean_Logic/04_Or/Or_tb.gtkw

@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Thu Dec 22 14:50:31 2022
+[*]
+[dumpfile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/04_Or/Or_tb.vcd"
+[dumpfile_mtime] "Thu Dec 22 14:50:17 2022"
+[dumpfile_size] 999
+[savefile] "/home/micha/gitlab/nand2tetris/01_Boolean_Logic/04_Or/Or_tb.gtkw"
+[timestart] 0
+[size] 1292 600
+[pos] -1 -1
+*-0.771027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 281
+[signals_width] 100
+[sst_expanded] 1
+[sst_vpaned_height] 132
+@200
+-IN
+@28
+Or_tb.a
+Or_tb.b
+@200
+-OUT
+@28
+Or_tb.out
+@200
+-CMP
+@29
+Or_tb.out_cmp
+@200
+-Test
+@28
+Or_tb.fail
+[pattern_trace] 1
+[pattern_trace] 0

01_Boolean_Logic/04_Or/Or_tb.v

@@ -0,0 +1,48 @@
+`default_nettype none
+module Or_tb();
+
+	// IN,OUT
+	reg a,b;
+	wire out;
+
+	// Part
+	Or OR(
+		.a(a),
+		.b(b),
+		.out(out)
+	);
+
+	// Compare
+	wire out_cmp;
+	assign out_cmp = a|b;
+
+	reg fail=0;
+	task check;
+		#1
+		if (out != out_cmp) 
+			begin
+				$display("FAIL: a=%1b, b=%1b, out=%1b",a,b,out);
+				fail=1;
+			end
+	endtask
+	  
+  	// Test
+	initial begin
+  		$dumpfile("Or_tb.vcd");
+  		$dumpvars(0, Or_tb);
+		
+		$display("------------------------");
+		$display("Testbench: Or");
+		
+		a=0;b=0;check();
+		a=0;b=1;check();
+		a=1;b=0;check();
+		a=1;b=1;check();
+		
+		if (fail==0) $display("passed");
+		$display("------------------------");
+		
+		$finish;
+	end
+
+endmodule

01_Boolean_Logic/04_Or/apio.ini

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+[env]
+board = iCE40-HX1K-EVB
+

01_Boolean_Logic/04_Or/iCE40HX1K.pcf

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+# physical constrain file
+# assign io-pins to pin numbering of iCE40-HX1K on olimex board iCE40-HX1K-EVB
+# compare to the schematic of the board and the datasheet of fpga
+
+set_io BUT1 41	# BUT1
+set_io BUT2 42	# BUT2
+
+set_io LED1 40	# LED1
+set_io LED2 51	# LED2
+

01_Boolean_Logic/04_Or/top.v

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+`default_nettype none
+module top(
+	input BUT1,
+	input BUT2,
+	output LED1,
+	output LED2
+);
+
+	Or OR(.a(BUT1),.b(BUT2),.out(LED1));
+	
+endmodule