add verilog files for project one through five

This commit is contained in:
2024-10-17 14:36:58 -04:00
parent b16bfcfd43
commit 792efa70cd
37 changed files with 871 additions and 275 deletions

View File

@@ -3,3 +3,10 @@
// read the button state and output to led
// Put your code here:
@BUT
D=M
@LED
M=!D
@0
0;JMP

View File

@@ -31,8 +31,41 @@ M=1
// Put your code here:
@R2
M=0
@DEBUG2
M=0
@itr
M=0
// loop declaration
// D = R1 - itr
// if 0 jump to @STOP
// else continue
(LOOP)
@itr
D=M
@R0
D=M-D
@DEBUG0
M=D
@END
D;JEQ
// R2 = R0 + R2
// itr = itr + 1
@R1
D=M
@R2
DM=D+M
@DEBUG2
M=D
@itr
M=M+1
// back to loop declaration
@LOOP
0;JMP
// till here!