add verilog files for project one through five

03_Sequential_Logic/Register.v

@@ -7,12 +7,27 @@
 `default_nettype none
 
 module Register(
-	input clk,
-	input [15:0] in,
-	input load,
-	output [15:0] out
+    input clk,
+    input [15:0] in,
+    input load,
+    output [15:0] out
 );
 
-	// Put your code here:
-
+    // Put your code here:
+    Bit BITA(clk, in[0], load, out[0]);
+    Bit BITB(clk, in[1], load, out[1]);
+    Bit BITC(clk, in[2], load, out[2]);
+    Bit BITD(clk, in[3], load, out[3]);
+    Bit BITE(clk, in[4], load, out[4]);
+    Bit BITF(clk, in[5], load, out[5]);
+    Bit BITG(clk, in[6], load, out[6]);
+    Bit BITH(clk, in[7], load, out[7]);
+    Bit BITI(clk, in[8], load, out[8]);
+    Bit BITJ(clk, in[9], load, out[9]);
+    Bit BITK(clk, in[10], load, out[10]);
+    Bit BITL(clk, in[11], load, out[11]);
+    Bit BITM(clk, in[12], load, out[12]);
+    Bit BITN(clk, in[13], load, out[13]);
+    Bit BITO(clk, in[14], load, out[14]);
+    Bit BITP(clk, in[15], load, out[15]);
 endmodule