wip optimization on SPI/LCD
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3157b5306d
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3fd95eff64
@ -134,7 +134,7 @@ module HACK(
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Mux16 SWITCHD(ROM_DATA, inIO6, load_sram, instruction);
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Register SRAM_A(clk, outM, loadIO5, inIO5);
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SRAM_D SRAM_D(clk, loadIO6, outM, inIO6, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX);
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//LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK);
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LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK);
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Register DEBUG0(clk, outM, loadIOB, inIOB);
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Register DEBUG1(clk, outM, loadIOC, inIOC);
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@ -150,10 +150,10 @@ module HACK(
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//assign SRAM_WEX=0;
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//assign SRAM_OEX=0;
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//assign SRAM_CSX=0;
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assign LCD_DCX=0;
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assign LCD_SDO=0;
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assign LCD_SCK=0;
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assign LCD_CSX=0;
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// assign LCD_DCX=0;
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// assign LCD_SDO=0;
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// assign LCD_SCK=0;
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// assign LCD_CSX=0;
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assign RTP_SDO=0;
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assign RTP_SCK=0;
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endmodule
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@ -15,106 +15,65 @@
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* After 32 clock cycles transmission is completed and out[15] is set to 0.
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*/
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`default_nettype none
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module LCD(
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input clk, //clock 25 MHz
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input load, //start send command/byte over SPI
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input load16, //start send data (16 bits)
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input [15:0] in, //data to be send
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output reg [15:0] out, //data to be send
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output reg DCX, //SPI data/command not
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output reg CSX, //SPI chip select not
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output reg SDO, //SPI serial data out
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output reg SCK //SPI serial clock
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module LCD (
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input wire clk, // 25 MHz clock
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input wire load, // Start sending 8-bit command/data
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input wire load16, // Start sending 16-bit data
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input wire [15:0] in, // Data to be sent
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output reg [15:0] out, // Status output
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output reg DCX, // Data/Command select (1 = data, 0 = command)
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output reg CSX, // Chip select (active low)
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output reg SDO, // Serial data out (MOSI)
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output reg SCK // Serial clock
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);
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// Put your code here:
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reg [15:0] to_send;
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reg [3:0] nthbit=0;
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reg csx_low=0;
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reg is_data=0;
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reg active=0;
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reg active16=0;
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reg [4:0] is16;
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always @(posedge clk) begin
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SDO <= 0;
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reg [15:0] shift_reg = 16'b0;
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reg [3:0] bit_counter = 0;
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reg transmitting = 0;
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reg is_16bit = 0;
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initial begin
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CSX <= 1;
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DCX <= 0;
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SCK <= 0;
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CSX <= (csx_low) ? 0 : 1;
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DCX <= (is_data) ? 1 : 0;
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out <= (load || load16 || active || active16) ? 16'h8000 : 16'h0000;
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SDO <= 0;
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end
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if (load && ~active && ~active16) begin
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if (in[8]) begin
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csx_low <= 0;
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CSX <= 1;
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end else begin
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active <= 1;
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is16 <= 1;
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csx_low <= 1;
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CSX <= 0;
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is_data <= in[9];
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DCX <= in[9];
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to_send <= in;
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SDO <= in[7];
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end
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always @(posedge clk) begin
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// Default signal values
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SCK <= 0;
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SDO <= transmitting ? SDO : 0;
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out <= (transmitting || load || load16) ? 16'h8000 : 16'h0000;
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//CSX <= ~transmitting;
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// Handle new transmission start
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if ((load || load16) && ~transmitting) begin
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transmitting <= 1;
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bit_counter <= (load16) ? 15 : 7;
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shift_reg <= (load16) ? in : {8'b0, in[7:0]};
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is_16bit <= load16;
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DCX <= (load16) ? 1 : in[9]; // data if load16 or in[9] for load
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CSX <= 0;
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SDO <= (load16) ? in[15] : in[7]; // First bit to send
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end
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else if (load16 && ~active && ~active16) begin
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active16 <= 1;
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is16 <= 1;
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csx_low <= 1;
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to_send <= in;
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SDO <= in[15];
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end
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else if (active) begin
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// Continue shifting out bits
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else if (transmitting) begin
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SCK <= ~SCK;
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if ( is16 == 15) begin
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active <= 0;
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SDO <= to_send[0];
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if (SCK == 1) begin
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// Set next bit on falling edge
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SDO <= shift_reg[bit_counter - 1];
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bit_counter <= bit_counter - 1;
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end
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else begin
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is16 <= is16 + 1;
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SDO <= SDO;
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case (is16)
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2 : SDO <= to_send[6];
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4 : SDO <= to_send[5];
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6 : SDO <= to_send[4];
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8 : SDO <= to_send[3];
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10 : SDO <= to_send[2];
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12 : SDO <= to_send[1];
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14 : SDO <= to_send[0];
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endcase
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end
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end
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else if (active16) begin
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SCK <= ~SCK;
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if ( is16 == 31) begin
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active16 <= 0;
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SDO <= to_send[0];
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end
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else begin
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is16 <= is16 + 1;
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SDO <= SDO;
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case (is16)
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2 : SDO <= to_send[14];
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4 : SDO <= to_send[13];
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6 : SDO <= to_send[12];
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8 : SDO <= to_send[11];
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10 : SDO <= to_send[10];
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12 : SDO <= to_send[9];
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14 : SDO <= to_send[8];
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16 : SDO <= to_send[7];
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18 : SDO <= to_send[6];
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20 : SDO <= to_send[5];
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22 : SDO <= to_send[4];
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24 : SDO <= to_send[3];
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26 : SDO <= to_send[2];
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28 : SDO <= to_send[1];
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30 : SDO <= to_send[0];
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endcase
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// Shift on rising edge
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if (bit_counter == 0 && SCK == 0) begin
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transmitting <= 0;
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end
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end
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end
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end
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endmodule
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@ -26,10 +26,10 @@ module SPI(
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reg [2:0] bit_index;
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reg [7:0] shift_out;
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reg [7:0] shift_in;
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reg [4:0] count;
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reg [3:0] count;
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wire is_sample_phase = (count >= 1 && count <= 15 && count[0] == 1);
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wire is_shift_phase = (count >= 2 && count <= 16 && count[0] == 0);
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wire is_shift_phase = (count >= 0 && count <= 14 && count[0] == 0);
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initial begin
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SDO <= 0;
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@ -47,7 +47,7 @@ module SPI(
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if (!in[8]) begin
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active <= 1;
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count <= 1;
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count <= 0;
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bit_index <= 7; // byte order MSB->LSB
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CSX <= 0;
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out[15] <= 1;
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@ -59,7 +59,7 @@ module SPI(
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else if (active==1) begin
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SCK <= ~SCK;
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if (count == 16) begin
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if (count == 15) begin
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SDO <= 0;
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out <= {8'b0, shift_in};
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@ -67,16 +67,15 @@ module SPI(
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end else begin
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count <= count + 1;
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if (is_shift_phase) begin
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// bit_index = bit_index - 1
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bit_index <= 7 - ((count) >> 1);
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if (is_sample_phase) begin
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bit_index <= bit_index - 1;
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out[7:0] <= {out[6:0], shift_in[bit_index]};
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shift_out <= {shift_out[6:0], 1'b0};
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SDO <= shift_out[6]; // next bit
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end
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if (is_sample_phase) begin
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if (is_shift_phase) begin
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shift_in[bit_index] <= SDI;
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end
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end
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