77 lines
1.5 KiB
Coq
77 lines
1.5 KiB
Coq
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`timescale 10ns/1ns
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`default_nettype none
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module UartRX_tb();
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// IN,OUT
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reg clk = 0;
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reg clear = 0;
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wire RX;
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wire [15:0] out;
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// Part
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UartRX UARTRX(
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.clk(clk),
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.clear(clear),
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.RX(RX),
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.out(out)
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);
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// Simulate
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always #2 clk=~clk;
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wire trigger;
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reg load=0;
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assign trigger = (n==1000) || (n==5000) || (n==9000);
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reg [15:0] in=0;
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always @(posedge clk) begin
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in <= trigger?$random:in;
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load <= trigger;
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clear <= (n==200);
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end
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// Compare
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reg [9:0] uart=10'b1111111111;
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reg [15:0] baudrate = 0;
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reg [15:0] bits = 0;
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always @(posedge clk)
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bits <= (load&~out_tx)?0:((baudrate==216)?bits+1:bits);
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always @(posedge clk)
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baudrate <= (load&~out_tx)?0:((baudrate==216)?0:(out_tx)?baudrate+1:baudrate);
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always @(posedge clk)
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uart <= (load&~out_tx)?((in<<2)|1):((baudrate==216)?{1'b1,uart[9:1]}:uart);
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reg out_tx = 0;
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always @(posedge clk)
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out_tx <= load?1:((bits==10)?0:out_tx);
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assign RX = uart[1];
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reg [15:0] out_cmp =0;
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always @(posedge clk)
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out_cmp <= clear?16'b1000000000000000:((baudrate==216)&(bits==9)?in& 16'h00ff:out_cmp);
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reg fail = 0;
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reg [31:0] n = 0;
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task check;
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#4
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if (out_cmp != out)
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begin
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$display("FAIL: clk=%1b, out=%16b",clk,out);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("UartRX_tb.vcd");
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$dumpvars(0, UartRX_tb);
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$display("------------------------");
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$display("Testbench: UartRX");
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for (n=0; n<10000;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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