// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM16K.hdl

/**
 * Memory of 16K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM16K {
    IN in[16], load, address[14];
    OUT out[16];

    PARTS:
    // Put your code here:
    DMux4Way(in=load, sel=address[12..13], a=toRAM4KA,
                                           b=toRAM4KB,
                                           c=toRAM4KC,
                                           d=toRAM4KD);

    RAM4K(in=in, load=toRAM4KA, address=address[0..11], out=fromRAM4KA);
    RAM4K(in=in, load=toRAM4KB, address=address[0..11], out=fromRAM4KB);
    RAM4K(in=in, load=toRAM4KC, address=address[0..11], out=fromRAM4KC);
    RAM4K(in=in, load=toRAM4KD, address=address[0..11], out=fromRAM4KD);

    Mux4Way16(sel=address[12..13], out=out, a=fromRAM4KA,
                                            b=fromRAM4KB,
                                            c=fromRAM4KC,
                                            d=fromRAM4KD);
}