46 lines
2.1 KiB
Plaintext
46 lines
2.1 KiB
Plaintext
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// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/03/b/RAM4K.hdl
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/**
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* Memory of 4K registers, each 16 bit-wide. Out holds the value
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* stored at the memory location specified by address. If load==1, then
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* the in value is loaded into the memory location specified by address
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* (the loaded value will be emitted to out from the next time step onward).
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*/
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CHIP RAM4K {
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IN in[16], load, address[12];
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OUT out[16];
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PARTS:
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// Put your code here:
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DMux8Way(in=load, sel=address[9..11], a=toRAM512A,
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b=toRAM512B,
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c=toRAM512C,
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d=toRAM512D,
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e=toRAM512E,
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f=toRAM512F,
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g=toRAM512G,
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h=toRAM512H);
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RAM512(in=in, load=toRAM512A, address=address[0..8], out=fromRAM512A);
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RAM512(in=in, load=toRAM512B, address=address[0..8], out=fromRAM512B);
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RAM512(in=in, load=toRAM512C, address=address[0..8], out=fromRAM512C);
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RAM512(in=in, load=toRAM512D, address=address[0..8], out=fromRAM512D);
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RAM512(in=in, load=toRAM512E, address=address[0..8], out=fromRAM512E);
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RAM512(in=in, load=toRAM512F, address=address[0..8], out=fromRAM512F);
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RAM512(in=in, load=toRAM512G, address=address[0..8], out=fromRAM512G);
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RAM512(in=in, load=toRAM512H, address=address[0..8], out=fromRAM512H);
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Mux8Way16(sel=address[9..11], out=out, a=fromRAM512A,
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b=fromRAM512B,
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c=fromRAM512C,
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d=fromRAM512D,
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e=fromRAM512E,
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f=fromRAM512F,
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g=fromRAM512G,
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h=fromRAM512H);
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}
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