38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
`default_nettype none
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module CPU(
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input clk,
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input [15:0] inM,
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input [15:0] instruction,
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input reset,
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output [15:0] outM,
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output writeM,
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output [15:0] addressM,
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output [15:0] pc
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);
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// Compare
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reg [15:0] addressM=0;
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reg [15:0] regD=0;
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reg [15:0] pc=0;
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wire [15:0] x,y;
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wire zr,ng;
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assign x = instruction[10]?(instruction[11]?~0:~regD):(instruction[11]?0:regD);
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assign y = instruction[8]?(instruction[9]?~0:~(instruction[12]?inM:addressM)):(instruction[9]?0:(instruction[12]?inM:addressM));
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assign outM = instruction[6]?(instruction[7]?~(x+y):~(x&y)):(instruction[7]?(x+y):(x&y));
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wire comp;
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wire jmp;
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assign comp = instruction[15] && instruction[14] && instruction[13];
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assign zr = (outM==0);
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assign ng = outM[15];
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assign jmp = comp && ((ng&&instruction[2])||(zr&&instruction[1])||(~(ng|zr)&&instruction[0]));
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always @(posedge clk) begin
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addressM <= comp?(instruction[5]?outM:addressM) : instruction;
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regD <= comp?(instruction[4]?outM:regD) : regD;
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pc <= reset?0 : (jmp?addressM:pc+1);
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end
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wire writeM;
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assign writeM = comp?instruction[3]:0;
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endmodule
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