21 lines
494 B
Verilog
21 lines
494 B
Verilog
/**
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* UartRX receives bytes over UART
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*
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* When clear = 1 the chip clears the receive buffer and is ready to receive
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* next byte. out[15] is set to 1 to show, that chip is ready to receive next
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* byte. When RX goes low the chip starts sampling the RX line. After reading
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* of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
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*/
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`default_nettype none
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module UartRX(
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input clk,
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input clear,
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input RX,
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output [15:0] out
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);
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// Put your code here:
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endmodule
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