19 lines
289 B
Verilog
19 lines
289 B
Verilog
/**
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* GO switches from boot to run mode.
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*/
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`default_nettype none
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module GO(
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input clk,
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input load,
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input [15:0] pc,
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input [15:0] sram_addr,
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output [15:0] SRAM_ADDR,
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input [15:0] sram_data,
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input [15:0] ROM_data,
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output [15:0] instruction
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);
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// Put your code here:
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endmodule
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