181 lines
4.4 KiB
Verilog
181 lines
4.4 KiB
Verilog
`default_nettype none
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module Memory_tb();
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// IN,OUT
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reg [15:0] address;
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reg load;
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wire [15:0] out;
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wire loadRAM;
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wire loadIO0;
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wire loadIO1;
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wire loadIO2;
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wire loadIO3;
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wire loadIO4;
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wire loadIO5;
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wire loadIO6;
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wire loadIO7;
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wire loadIO8;
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wire loadIO9;
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wire loadIOA;
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wire loadIOB;
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wire loadIOC;
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wire loadIOD;
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wire loadIOE;
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wire loadIOF;
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reg [15:0] inRAM;
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reg [15:0] inIO0;
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reg [15:0] inIO1;
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reg [15:0] inIO2;
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reg [15:0] inIO3;
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reg [15:0] inIO4;
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reg [15:0] inIO5;
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reg [15:0] inIO6;
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reg [15:0] inIO7;
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reg [15:0] inIO8;
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reg [15:0] inIO9;
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reg [15:0] inIOA;
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reg [15:0] inIOB;
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reg [15:0] inIOC;
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reg [15:0] inIOD;
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reg [15:0] inIOE;
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reg [15:0] inIOF;
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// Part
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Memory MEMORY(
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.address(address),
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.load(load),
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.out(out),
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.loadRAM(loadRAM),
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.loadIO0(loadIO0),
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.loadIO1(loadIO1),
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.loadIO2(loadIO2),
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.loadIO3(loadIO3),
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.loadIO4(loadIO4),
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.loadIO5(loadIO5),
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.loadIO6(loadIO6),
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.loadIO7(loadIO7),
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.loadIO8(loadIO8),
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.loadIO9(loadIO9),
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.loadIOA(loadIOA),
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.loadIOB(loadIOB),
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.loadIOC(loadIOC),
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.loadIOD(loadIOD),
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.loadIOE(loadIOE),
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.loadIOF(loadIOF),
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.inRAM(inRAM),
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.inIO0(inIO0),
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.inIO1(inIO1),
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.inIO2(inIO2),
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.inIO3(inIO3),
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.inIO4(inIO4),
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.inIO5(inIO5),
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.inIO6(inIO6),
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.inIO7(inIO7),
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.inIO8(inIO8),
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.inIO9(inIO9),
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.inIOA(inIOA),
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.inIOB(inIOB),
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.inIOC(inIOC),
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.inIOD(inIOD),
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.inIOE(inIOE),
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.inIOF(inIOF)
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);
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// Compare
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reg fail = 0;
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wire [15:0] out_cmp;
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assign out_cmp = ((address==4096)?inIO0:
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(address==4097)?inIO1:
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(address==4098)?inIO2:
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(address==4099)?inIO3:
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(address==4100)?inIO4:
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(address==4101)?inIO5:
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(address==4102)?inIO6:
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(address==4103)?inIO7:
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(address==4104)?inIO8:
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(address==4105)?inIO9:
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(address==4106)?inIOA:
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(address==4107)?inIOB:
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(address==4108)?inIOC:
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(address==4109)?inIOD:
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(address==4110)?inIOE:
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(address==4111)?inIOF:
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inRAM);
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wire loadRAM_cmp,loadIO0_cmp,loadIO1_cmp,loadIO2_cmp,loadIO3_cmp,loadIO4_cmp,loadIO5_cmp,loadIO6_cmp,loadIO7_cmp,
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loadIO8_cmp,loadIO9_cmp,loadIOA_cmp,loadIOB_cmp,loadIOC_cmp,loadIOD_cmp,loadIOE_cmp,loadIOF_cmp;
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assign loadRAM_cmp = (address<=3839)?load:0;
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assign loadIO0_cmp = (address==4096)?load:0;
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assign loadIO1_cmp = (address==4097)?load:0;
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assign loadIO2_cmp = (address==4098)?load:0;
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assign loadIO3_cmp = (address==4099)?load:0;
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assign loadIO4_cmp = (address==4100)?load:0;
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assign loadIO5_cmp = (address==4101)?load:0;
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assign loadIO6_cmp = (address==4102)?load:0;
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assign loadIO7_cmp = (address==4103)?load:0;
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assign loadIO8_cmp = (address==4104)?load:0;
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assign loadIO9_cmp = (address==4105)?load:0;
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assign loadIOA_cmp = (address==4106)?load:0;
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assign loadIOB_cmp = (address==4107)?load:0;
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assign loadIOC_cmp = (address==4108)?load:0;
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assign loadIOD_cmp = (address==4109)?load:0;
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assign loadIOE_cmp = (address==4110)?load:0;
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assign loadIOF_cmp = (address==4111)?load:0;
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task check;
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#1
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if ((out!=out_cmp)||(loadRAM!=loadRAM_cmp)||
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(loadIO0!=loadIO0_cmp)||(loadIO1!=loadIO1_cmp)||(loadIO2!=loadIO2_cmp)||(loadIO3!=loadIO3_cmp)||
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(loadIO4!=loadIO4_cmp)||(loadIO5!=loadIO5_cmp)||(loadIO6!=loadIO6_cmp)||(loadIO7!=loadIO7_cmp)||
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(loadIO8!=loadIO8_cmp)||(loadIO9!=loadIO9_cmp)||(loadIOA!=loadIOA_cmp)||(loadIOB!=loadIOB_cmp)||
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(loadIOC!=loadIOC_cmp)||(loadIOD!=loadIOD_cmp)||(loadIOE!=loadIOE_cmp)||(loadIOF!=loadIOF_cmp))
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begin
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$display("FAIL: address=%16b, load=%1b, out=%16b, loadRAM=%1b, loadIO0=%1b, loadIO1=%1b, ... ",address,load,out,loadRAM,loadIO0,loadIO1);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("Memory_tb.vcd");
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$dumpvars(0, Memory_tb);
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$display("------------------------");
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$display("Testbench: Memory");
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inRAM=$random;
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inIO0=$random;
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inIO1=$random;
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inIO2=$random;
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inIO3=$random;
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inIO4=$random;
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inIO5=$random;
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inIO6=$random;
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inIO7=$random;
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inIO8=$random;
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inIO9=$random;
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inIOA=$random;
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inIOB=$random;
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inIOC=$random;
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inIOD=$random;
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inIOE=$random;
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inIOF=$random;
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for (address=4096; address<4112;address=address+1)
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begin
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load=0;check();
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load=1;check();
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end
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for (address=0; address<3840;address=address+1)
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begin
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inRAM=$random;
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load=0;check();
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load=1;check();
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end
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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