75 lines
1.4 KiB
Verilog
75 lines
1.4 KiB
Verilog
`default_nettype none
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module DMux8Way_tb();
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// IN,OUT
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reg in;
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reg [2:0] sel;
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wire a,b,c,d,e,f,g,h;
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// Part
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DMux8Way DMUX8WAY(
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.in(in),
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.sel(sel),
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.a(a),
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.b(b),
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.c(c),
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.d(d),
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.e(e),
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.f(f),
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.g(g),
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.h(h)
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);
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// Compare
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wire a_cmp,b_cmp,c_cmp,d_cmp,e_cmp,f_cmp,g_cmp,h_cmp;
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assign a_cmp = (sel==0)?in:0;
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assign b_cmp = (sel==1)?in:0;
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assign c_cmp = (sel==2)?in:0;
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assign d_cmp = (sel==3)?in:0;
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assign e_cmp = (sel==4)?in:0;
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assign f_cmp = (sel==5)?in:0;
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assign g_cmp = (sel==6)?in:0;
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assign h_cmp = (sel==7)?in:0;
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reg fail = 0;
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task check;
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#1
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if ((a!=a_cmp)||(b!=b_cmp)||(c!=c_cmp)||(d!=d_cmp)||(e!=e_cmp)||(f!=f_cmp)||(g!=g_cmp)||(h!=h_cmp))
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begin
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$display("FAIL: in=%1b, sel=%2b, a=%1b, b=%1b, c=%1b, d=%1b, e=%1b, f=%1b, g=%1b, h=%1b",in,sel,a,b,c,d,e,f,g,h);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("DMux8Way_tb.vcd");
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$dumpvars(0, DMux8Way_tb);
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$display("------------------------");
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$display("Testbench: DMux8Way");
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in=0;sel=0;check();
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in=0;sel=1;check();
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in=0;sel=2;check();
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in=0;sel=3;check();
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in=0;sel=4;check();
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in=0;sel=5;check();
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in=0;sel=6;check();
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in=0;sel=7;check();
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in=1;sel=0;check();
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in=1;sel=1;check();
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in=1;sel=2;check();
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in=1;sel=3;check();
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in=1;sel=4;check();
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in=1;sel=5;check();
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in=1;sel=6;check();
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in=1;sel=7;check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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