21 lines
350 B
Verilog
21 lines
350 B
Verilog
/**
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* One Bit-register, that can be switched on and off
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*
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* if (out[t] == 0) and (on[t] == 1) out[t+1] = 1
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* if (out[t] == 1) and (off[t] == 1) out[t+1] = 0
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*/
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`default_nettype none
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module Switch(
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input clk,
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input on,
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input off,
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output out
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);
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reg out = 0;
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always @(posedge clk)
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out <= (on&off)?(~out):(on?1:(off?0:(out?1:0)));
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endmodule
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