22 lines
556 B
Verilog
22 lines
556 B
Verilog
/**
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* UartTX controls transmission of bytes over UART.
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*
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* When load = 1 the chip starts serial transmission of the byte in[7:0] to the
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* TX line according to the protocoll 8N1 with 115200 baud. During transmission
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* out[15] is set to high (busy). The transmission is finished after 2170 clock
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* cycles (10 byte a 217 cycle each). When transmission completes out[15] goes
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* low again (ready).
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*/
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`default_nettype none
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module UartTX(
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input clk,
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input load,
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input [15:0] in,
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output TX,
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output [15:0] out
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);
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// Put your code here:
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endmodule
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