17 lines
234 B
Verilog
17 lines
234 B
Verilog
/**
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* Adds two 16-bit values.
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* The most significant carry bit is ignored.
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* out = a + b (16 bit)
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*/
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`default_nettype none
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module Add16(
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input [15:0] a,
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input [15:0] b,
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output [15:0] out
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);
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// Put your code here:
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endmodule
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