52 lines
740 B
Verilog
52 lines
740 B
Verilog
`default_nettype none
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module And16_tb();
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// IN,OUT
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reg [15:0] a,b;
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wire [15:0] out;
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// Part
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And16 AND16(
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.a(a),
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.b(b),
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.out(out)
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);
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// Compare
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wire [15:0] out_cmp;
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assign out_cmp = a&b;
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reg fail = 0;
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reg [15:0] n = 0;
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task check;
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#1
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if (out != out_cmp)
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begin
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$display("FAIL: a=%16b, b=%16b, out=%16b",a,b,out);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("And16_tb.vcd");
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$dumpvars(0, And16_tb);
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$display("------------------------");
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$display("Testbench: And16");
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for (n=0; n<10000;n=n+1)
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begin
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a=$random;
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b=$random;
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check();
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end
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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