50 lines
753 B
Verilog
50 lines
753 B
Verilog
`default_nettype none
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module DMux_tb();
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// IN,OUT
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reg in,sel;
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wire a,b;
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// Part
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DMux DMUX(
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.in(in),
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.sel(sel),
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.a(a),
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.b(b)
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);
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// Compare
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wire a_cmp,b_cmp;
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assign a_cmp = (~sel&in);
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assign b_cmp = sel∈
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reg fail=0;
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task check;
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#1
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if ((a != a_cmp) || (b != b_cmp))
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begin
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$display("FAIL: in=%1b, sel=%1b, a=%1b, b=%1b",in,sel,a,b);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("DMux_tb.vcd");
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$dumpvars(0, DMux_tb);
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$display("------------------------");
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$display("Testbench: DMux");
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in=0;sel=0;check();
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in=0;sel=1;check();
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in=1;sel=0;check();
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in=1;sel=1;check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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