18 lines
262 B
Verilog
18 lines
262 B
Verilog
/**
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* 16-bit multiplexor:
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* for i = 0..15 out[i] = a[i] if sel == 0
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* b[i] if sel == 1
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*/
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`default_nettype none
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module Mux16(
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input [15:0] a,
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input [15:0] b,
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input sel,
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output [15:0] out
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);
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assign out = sel?b:a;
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endmodule
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