74 lines
1.3 KiB
Verilog
74 lines
1.3 KiB
Verilog
`timescale 10ns/1ns
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`default_nettype none
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module GO_tb();
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// IN,OUT
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reg clk = 0;
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reg load = 0;
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reg [15:0] sram_addr=0;
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reg [15:0] pc=0;
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wire [15:0] SRAM_ADDR;
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reg [15:0] ROM_data=0;
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reg [15:0] sram_data=0;
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wire [15:0] instruction;
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// Part
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GO GO(
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.clk(clk),
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.load(load),
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.sram_addr(sram_addr),
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.pc(pc),
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.SRAM_ADDR(SRAM_ADDR),
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.ROM_data(ROM_data),
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.sram_data(sram_data),
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.instruction(instruction)
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);
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// Simulate
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always #2 clk=~clk;
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wire trigger;
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reg write;
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assign trigger = (n==10);
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always @(posedge clk) begin
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sram_addr <= $random;
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pc <= $random;
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ROM_data <= $random;
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sram_data <= $random;
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load <= trigger;
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end
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// Compare
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reg fail = 0;
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reg [31:0] n = 0;
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reg run=0;
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always @(posedge clk)
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if (load) run <=1;
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wire [15:0] SRAM_ADDR_cmp=run?pc:sram_addr;
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wire [15:0] instruction_cmp=run?sram_data:ROM_data;
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task check;
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#4
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if ((SRAM_ADDR!=SRAM_ADDR_cmp) || (instruction!=instruction_cmp))
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begin
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$display("FAIL: clk=%1b, load=%1b",clk,load);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("GO_tb.vcd");
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$dumpvars(0, GO_tb);
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$display("------------------------");
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$display("Testbench: GO");
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for (n=0; n<20;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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