16 lines
339 B
Verilog
16 lines
339 B
Verilog
/**
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* Uses CLK of 100MHz to generate:
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* internal clock signal clk with 25MHz and
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* a reset signal of approx. 20us length
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*/
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`default_nettype none
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module Clock25_Reset20(
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input CLK, // external clock 100 MHz
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output clk, // internal clock 25 Mhz
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output reset // reset signal approx. 20us
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);
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// Put your code here:
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endmodule
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