21 lines
302 B
Verilog
21 lines
302 B
Verilog
/**
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* Data-Flip-Flop
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* out[t+1] = in[t]
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*/
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`default_nettype none
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module DFF(
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input clk,
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input in,
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output out
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);
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// No need to implement this chip
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// This chip is implemented in verilog using reg-variables
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reg out;
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always @(posedge clk)
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if (in) out <= 1'b1;
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else out <= 1'b0;
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endmodule
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