48 lines
748 B
Verilog
48 lines
748 B
Verilog
`default_nettype none
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module HalfAdder_tb();
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// IN,OUT
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reg a,b;
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wire sum,carry;
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// Part
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HalfAdder HALFADDER(
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.a(a),
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.b(b),
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.sum(sum),
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.carry(carry)
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);
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// Compare
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wire [1:0] out_cmp;
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assign out_cmp = a+b;
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reg fail = 0;
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task check;
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#1
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if ({carry,sum} != out_cmp)
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begin
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$display("FAIL: a=%1b, b=%1b, sum=%1b, carry=%1b",a,b,sum,carry);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("HalfAdder_tb.vcd");
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$dumpvars(0, HalfAdder_tb);
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$display("------------------------");
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$display("Testbench: HalfAdder");
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a=0;b=0;check();
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a=0;b=1;check();
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a=1;b=0;check();
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a=1;b=1;check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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