15 lines
183 B
Verilog
15 lines
183 B
Verilog
/**
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* 16-bit bitwise Buffer:
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* for i = 0..15: out[i] = in[i]
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*/
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`default_nettype none
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module Buffer16(
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input [15:0] in,
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output [15:0] out
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);
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// Put your code here:
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endmodule
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