23 lines
486 B
Verilog
23 lines
486 B
Verilog
/**
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* A 16-bit counter with load and reset control bits.
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* if (reset[t] == 1) out[t+1] = 0
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* else if (load[t] == 1) out[t+1] = in[t]
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* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
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* else out[t+1] = out[t]
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*/
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`default_nettype none
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module PC(
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input clk,
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input [15:0] in,
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input load,
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input inc,
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input reset,
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output [15:0] out
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);
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reg [15:0] out = 0;
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always @(posedge clk)
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out <= reset?0:(load?in:(inc?out+1:out));
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endmodule
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