15 lines
188 B
Verilog
15 lines
188 B
Verilog
/**
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* 8-way Or:
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* out = (in[0] or in[1] or ... or in[7])
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*/
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`default_nettype none
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module Or8Way(
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input [7:0] in,
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output out
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);
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// Put your code here:
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assign out = |in;
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endmodule
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