33 lines
528 B
Verilog
33 lines
528 B
Verilog
/**
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* 16-bit multiplexor:
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* for i = 0..15 out[i] = a[i] if sel == 0
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* b[i] if sel == 1
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*/
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`default_nettype none
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module Mux8Way16(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [15:0] d,
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input [15:0] e,
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input [15:0] f,
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input [15:0] g,
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input [15:0] h,
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input [2:0] sel,
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output reg [15:0] out
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);
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always @(*) begin
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case (sel)
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0 : out = a;
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1 : out = b;
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2 : out = c;
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3 : out = d;
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4 : out = e;
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5 : out = f;
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6 : out = g;
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7 : out = h;
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endcase
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end
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endmodule
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