20 lines
276 B
Verilog
20 lines
276 B
Verilog
/**
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* 1-bit register:
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* If load[t] == 1 then out[t+1] = in[t]
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* else out does not change (out[t+1] = out[t])
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*/
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`default_nettype none
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module Bit(
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input clk,
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input in,
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input load,
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output out
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);
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reg out = 0;
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always @(posedge clk)
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out <= load?in:out;
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endmodule
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