82 lines
1.6 KiB
Verilog
82 lines
1.6 KiB
Verilog
`timescale 10ns/1ns
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`default_nettype none
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module RTP_tb();
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// IN,OUT
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reg clk = 0;
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reg load = 0;
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reg [15:0] in = 0;
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wire [15:0] out;
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wire SDO;
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reg SDI=0;
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wire SCK;
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// Part
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RTP RTP(
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.clk(clk),
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.load(load),
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.in(in),
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.out(out),
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.SDO(SDO),
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.SDI(SDI),
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.SCK(SCK)
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);
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// Simulate
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always #2 clk=~clk;
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wire trigger;
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assign trigger = (n==20) || (n==420) || (n==820) || (n==1220) || (n==1620);
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always @(posedge clk) begin
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in <= trigger?$random&16'h03ff:in;
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load <= trigger;
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end
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always @(posedge SCK_cmp)
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SDI <= $random;
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// Compare
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reg[8:0] bits=0;
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always @(posedge clk)
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bits <= load?1:((bits==256)?0:(busy?bits+1:0));
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wire busy=|bits[8:0];
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wire [15:0] out_cmp = {busy,7'd0,shift};
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reg [7:0] shift=0;
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wire tr=~|bits[3:0]&busy;
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reg lsb=0;
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always @(posedge clk)
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lsb<=(tr&SCK_cmp)?SDI:lsb;
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always @(posedge clk)
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shift <= load?in[7:0]:((tr&~SCK_cmp)?{shift[6:0],lsb}:shift);
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reg SCK_cmp=0;
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always @(posedge clk)
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SCK_cmp <= load?1:(tr&busy&~bits[8])?~SCK_cmp:SCK_cmp;
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wire SDO_cmp;
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assign SDO_cmp = shift[7];
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reg fail = 0;
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reg [31:0] n = 0;
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task check;
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#4
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if ((out!=out_cmp)||(SCK!=SCK_cmp)||(SDO!=SDO_cmp))
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begin
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$display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, SDO=%1b, SDI=%1b, SCK=%1b",clk,load,in,out,SDO,SDI,SCK);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("RTP_tb.vcd");
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$dumpvars(0, RTP_tb);
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$display("------------------------");
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$display("Testbench: RTP");
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for (n=0; n<2000;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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