33 lines
480 B
Verilog
33 lines
480 B
Verilog
`timescale 10ns/1ns
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`default_nettype none
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module Clock25_Reset20_tb();
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// IN,OUT
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reg CLK=1;
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wire clk;
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wire reset;
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// Part
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Clock25_Reset20 CLOCK25_RESET20(
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.CLK(CLK),
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.clk(clk),
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.reset(reset)
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);
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// Simulation
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always #0.5 CLK=~CLK;
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// Test
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initial begin
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$dumpfile("Clock25_Reset20_tb.vcd");
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$dumpvars(0, Clock25_Reset20_tb);
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$display("------------------------");
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$display("Testbench: Clock25_Reset10");
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#4000
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$finish;
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end
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endmodule
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