61 lines
1.5 KiB
Verilog
61 lines
1.5 KiB
Verilog
/**
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* The complete address space of the Hack computer's memory,
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* including RAM and memory-mapped I/O.
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* The chip facilitates read and write operations, as follows:
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* Read: out(t) = Memory[address(t)](t)
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* Write: if load(t-1) then Memory[address(t-1)](t) = in(t-1)
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* In words: the chip always outputs the value stored at the memory
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* location specified by address. If load==1, the in value is loaded
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* into the memory location specified by address. This value becomes
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* available through the out output from the next time step onward.
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* Address space rules:
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* RAM 0x0000 - 0x0EFF (3840 words)
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* IO 0x1000 - 0x100F (maps to 16 different devices)
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* The behavior of IO addresses is described in 06_IO-Devices
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*/
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`default_nettype none
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module Memory(
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input [15:0] address,
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input load,
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output [15:0] out,
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output loadRAM,
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output loadIO0,
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output loadIO1,
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output loadIO2,
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output loadIO3,
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output loadIO4,
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output loadIO5,
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output loadIO6,
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output loadIO7,
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output loadIO8,
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output loadIO9,
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output loadIOA,
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output loadIOB,
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output loadIOC,
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output loadIOD,
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output loadIOE,
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output loadIOF,
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input [15:0] inRAM,
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input [15:0] inIO0,
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input [15:0] inIO1,
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input [15:0] inIO2,
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input [15:0] inIO3,
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input [15:0] inIO4,
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input [15:0] inIO5,
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input [15:0] inIO6,
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input [15:0] inIO7,
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input [15:0] inIO8,
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input [15:0] inIO9,
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input [15:0] inIOA,
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input [15:0] inIOB,
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input [15:0] inIOC,
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input [15:0] inIOD,
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input [15:0] inIOE,
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input [15:0] inIOF
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);
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// Put your code here:
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endmodule
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