19 lines
295 B
Verilog
19 lines
295 B
Verilog
/**
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* RAM3840 implements 3840 Bytes of RAM addressed from 0 - 3839
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* out = M[address]
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* if (load =i= 1) M[address][t+1] = in[t]
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*/
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`default_nettype none
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module RAM3840(
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input clk,
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input [11:0] address,
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input [15:0] in,
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input load,
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output [15:0] out
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);
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// Put your code here:
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endmodule
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