17 lines
180 B
Verilog
17 lines
180 B
Verilog
/**
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* Or gate:
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* out = 1 if (a == 1 or b == 1)
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* 0 otherwise
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*/
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`default_nettype none
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module Or(
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input a,
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input b,
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output out
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);
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// Put your code here:
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endmodule
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