26 lines
475 B
Verilog
26 lines
475 B
Verilog
/**
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* 8-way demultiplexor:
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* {a, b, c, d, e, f, g, h} = {in, 0, 0, 0, 0, 0, 0, 0} if sel == 000
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* {0, in, 0, 0, 0, 0, 0, 0} if sel == 001
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* etc.
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* {0, 0, 0, 0, 0, 0, 0, in} if sel == 111
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*/
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`default_nettype none
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module DMux8Way(
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input in,
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input [2:0] sel,
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output a,
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output b,
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output c,
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output d,
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output e,
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output f,
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output g,
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output h
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);
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// Put your code here:
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endmodule
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