16 lines
203 B
Verilog
16 lines
203 B
Verilog
/**
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* 16-bit bitwise And:
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* for i = 0..15: out[i] = (a[i] and b[i])
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*/
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`default_nettype none
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module And16(
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input [15:0] a,
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input [15:0] b,
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output [15:0] out
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);
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// Put your code here:
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endmodule
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