55 lines
1.6 KiB
Verilog
55 lines
1.6 KiB
Verilog
/**
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* UartTX controls transmission of bytes over UART.
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*
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* When load = 1 the chip starts serial transmission of the byte in[7:0] to the
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* TX line according to the protocoll 8N1 with 115200 baud. During transmission
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* out[15] is set to high (busy). The transmission is finished after 2170 clock
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* cycles (10 byte a 217 cycle each). When transmission completes out[15] goes
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* low again (ready).
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*/
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`default_nettype none
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module UartTX(
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input clk,
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input load,
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input [15:0] in,
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output TX,
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output reg [15:0] out
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);
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reg uart=1;
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reg active=0;
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reg [7:0] to_send;
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reg [3:0] nthbit=0;
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reg [9:0] is216;
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always @(posedge clk) begin
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out <= (load || active) ? 16'h8000 : 16'h0000;
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if ((active==0) && (load == 1)) begin
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active <= 1;
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is216 <= 1;
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nthbit <= 0;
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uart <= 0;
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to_send <= in[7:0];
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end
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else if (active==1) begin
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is216 <= (is216 == 216) ? 0 : is216 + 1;
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nthbit <= (is216 == 216) ? nthbit + 1 : nthbit;
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case (nthbit)
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0 : uart <= 0;
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1 : uart <= to_send[0];
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2 : uart <= to_send[1];
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3 : uart <= to_send[2];
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4 : uart <= to_send[3];
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5 : uart <= to_send[4];
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6 : uart <= to_send[5];
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7 : uart <= to_send[6];
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8 : uart <= to_send[7];
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9 : uart <= 1;
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10 : begin active <= 0; out <= 16'h0000; end
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endcase
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end
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end
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assign TX = uart;
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endmodule
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