54 lines
1.5 KiB
Verilog
54 lines
1.5 KiB
Verilog
/**
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* UartRX receives bytes over UART
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*
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* When clear = 1 the chip clears the receive buffer and is ready to receive
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* next byte. out[15] is set to 1 to show, that chip is ready to receive next
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* byte. When RX goes low the chip starts sampling the RX line. After reading
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* of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
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*/
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`default_nettype none
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module UartRX(
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input clk,
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input clear,
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input RX,
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output reg [15:0] out
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);
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// Put your code here:
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wire clkdRX;
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reg active=0;
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reg out_set=0;
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reg [7:0] uart;
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reg [3:0] nthbit;
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reg [9:0] is216;
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always @(posedge clk) begin
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out_set <= clear ? 1 : out_set;
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out <= clear ? 16'h8000 : (out_set ? out : 16'h0000);
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if ((active==0) && (RX == 0)) begin
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out_set <=1;
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active <= 1;
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is216 <= 1;
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uart <= 0;
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nthbit <= 0;
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end
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else if (active==1) begin
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is216 <= (is216 == 216) ? 0 : is216 + 1;
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nthbit <= (is216 == 108) ? nthbit + 1 : nthbit;
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case (nthbit)
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1 : uart[0] <= RX;
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2 : uart[1] <= RX;
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3 : uart[2] <= RX;
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4 : uart[3] <= RX;
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5 : uart[4] <= RX;
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6 : uart[5] <= RX;
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7 : uart[6] <= RX;
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8 : uart[7] <= RX;
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endcase
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if (nthbit == 10 && is216 == 216) begin
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active <= 0;
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out <= {8'b0, uart};
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end
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end
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end
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endmodule
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