126 lines
3.8 KiB
Verilog
126 lines
3.8 KiB
Verilog
/**
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* SPI controller for W25Q16BV
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*
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* When load=1 transmission of byte in[7:0] is initiated. The byte is send to
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* MOSI (master out slave in) bitwise together with 8 clock signals on SCK.
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* At the same time the SPI recieves a byte at MISO (master in slave out).
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* Sampling of MISO is done at rising edge of SCK and shiftingis done at
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*/
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`default_nettype none
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module SPI(
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input clk,
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input load,
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input [15:0] in,
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output reg [15:0] out,
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output reg CSX,
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output reg SDO,
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input SDI,
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output reg SCK
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);
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// Put your code here:
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// 1100 0000 0101 1011
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// 1000 0000 0101 1011
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reg active=0;
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reg csx_low=0;
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reg out_low=1;
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reg [7:0] totx;
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reg [7:0] torx;
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reg [4:0] is16;
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always @(posedge clk) begin
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CSX <= (csx_low) ? 0 : 1;
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SDO <= 0;
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SCK <= 0;
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out <= (out)? out : 0;
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if (load == 1) begin
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out_low=0;
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out[14:8] <= 0;
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out[7:0] <= in[7:0];
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if (in[8]==1) begin
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out[15] <= 0;
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csx_low <= 0;
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CSX <= 1;
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end
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else if (in[8]==0) begin
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out[15] <= 1;
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csx_low <= 1;
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CSX <= 0;
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active <= 1;
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is16 <= 1;
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totx[7:0] <= in[7:0];
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SDO <= in[7];
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end
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end
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else if (active==1) begin
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SCK <= ~SCK;
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if (is16 == 16) begin
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active <= 0;
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out <= {8'b0, torx[7:0]};
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end
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else begin
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csx_low <= 1;
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is16 <= is16 + 1;
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case (is16+1)
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2 : SDO <= totx[7];
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3 : SDO <= totx[6];
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4 : SDO <= totx[6];
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5 : SDO <= totx[5];
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6 : SDO <= totx[5];
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7 : SDO <= totx[4];
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8 : SDO <= totx[4];
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9 : SDO <= totx[3];
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10 : SDO <= totx[3];
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11 : SDO <= totx[2];
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12 : SDO <= totx[2];
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13 : SDO <= totx[1];
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14 : SDO <= totx[1];
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15 : SDO <= totx[0];
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16 : SDO <= totx[0];
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endcase
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case (is16)
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1 : torx[7] <= SDI;
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3 : torx[6] <= SDI;
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5 : torx[5] <= SDI;
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7 : torx[4] <= SDI;
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9 : torx[3] <= SDI;
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11 : torx[2] <= SDI;
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13 : torx[1] <= SDI;
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15 : torx[0] <= SDI;
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endcase
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case (is16)
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2 : out <= (out<<1);
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4 : out <= (out<<1);
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6 : out <= (out<<1);
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8 : out <= (out<<1);
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10 : out <= (out<<1);
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12 : out <= (out<<1);
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14 : out <= (out<<1);
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endcase
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case (is16)
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2 : out[0] <= torx[7];
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4 : out[0] <= torx[6];
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6 : out[0] <= torx[5];
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8 : out[0] <= torx[4];
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10 : out[0] <= torx[3];
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12 : out[0] <= torx[2];
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14 : out[0] <= torx[1];
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endcase
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case (is16)
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2 : out[15:8] <= 8'b10000000;
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4 : out[15:8] <= 8'b10000000;
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6 : out[15:8] <= 8'b10000000;
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8 : out[15:8] <= 8'b10000000;
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10 : out[15:8] <= 8'b10000000;
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12 : out[15:8] <= 8'b10000000;
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14 : out[15:8] <= 8'b10000000;
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endcase
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end
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end else begin
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out <= out_low? 16'b0 : out;
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end
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end
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endmodule
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