28 lines
821 B
Verilog
28 lines
821 B
Verilog
/**
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* The special function register RTP receives bytes from the touch panel
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* controller AR1021.
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*
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* When load=1 transmission of byte in[7:0] is initiated. The byte is send to
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* SDO bitwise together with 8 clock signals on SCK. At the same time RTP
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* receives a byte at SDI. During transmission out[15] is 1. The transmission
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* of a byte takes 256 clock cycles (32 cycles for each bit to achieve a slower
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* transfer rate). Every 32 clock cycles one bit is shifted out. In the middle
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* of each bit at counter number 31 the bit SDI is sampled. When transmission
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* is completed out[15]=0 and RTP outputs the received byte to out[7:0].
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*/
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`default_nettype none
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module RTP(
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input clk,
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input load,
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input [15:0] in,
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output [15:0] out,
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output SDO,
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input SDI,
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output SCK
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);
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// Put your code here:
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endmodule
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