121 lines
3.9 KiB
Verilog
121 lines
3.9 KiB
Verilog
/*
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* LCD communicates with ILI9341V LCD controller over 4 wire SPI.
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*
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* When load=1 and in[8]=0 transmission of byte in[7:0] is initiated.
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* CSX is goes low (and stays low even when transmission is completed).
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* DCX is set to in[9]. The byte in[7:0] is send to SDO bitwise together
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* with 8 clock signals on SCK. During transmission out[15] is 1.
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* After 16 clock cycles transmission is completed and out[15] is set to 0.
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*
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* When load=1 and in[8]=1 CSX goes high and DCX=in[9] without transmission
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* of any bit.
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*
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* When load16=1 transmission of word in[15:0] is initiated. CSX is goes low
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* (and stays low even when transmission is completed). DCX is set to 1 (data).
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* After 32 clock cycles transmission is completed and out[15] is set to 0.
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*/
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`default_nettype none
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module LCD(
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input clk, //clock 25 MHz
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input load, //start send command/byte over SPI
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input load16, //start send data (16 bits)
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input [15:0] in, //data to be send
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output reg [15:0] out, //data to be send
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output reg DCX, //SPI data/command not
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output reg CSX, //SPI chip select not
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output reg SDO, //SPI serial data out
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output reg SCK //SPI serial clock
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);
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// Put your code here:
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reg [15:0] to_send;
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reg [3:0] nthbit=0;
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reg csx_low=0;
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reg is_data=0;
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reg active=0;
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reg active16=0;
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reg [4:0] is16;
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always @(posedge clk) begin
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SDO <= 0;
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SCK <= 0;
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CSX <= (csx_low) ? 0 : 1;
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DCX <= (is_data) ? 1 : 0;
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out <= (load || load16 || active || active16) ? 16'h8000 : 16'h0000;
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if (load && ~active && ~active16) begin
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if (in[8]) begin
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csx_low <= 0;
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CSX <= 1;
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end else begin
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active <= 1;
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is16 <= 1;
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csx_low <= 1;
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CSX <= 0;
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is_data <= in[9];
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DCX <= in[9];
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to_send <= in;
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SDO <= in[7];
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end
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end
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else if (load16 && ~active && ~active16) begin
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active16 <= 1;
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is16 <= 1;
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csx_low <= 1;
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to_send <= in;
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SDO <= in[15];
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end
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else if (active) begin
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SCK <= ~SCK;
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if ( is16 == 15) begin
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active <= 0;
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SDO <= to_send[0];
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end
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else begin
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is16 <= is16 + 1;
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SDO <= SDO;
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case (is16)
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2 : SDO <= to_send[6];
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4 : SDO <= to_send[5];
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6 : SDO <= to_send[4];
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8 : SDO <= to_send[3];
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10 : SDO <= to_send[2];
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12 : SDO <= to_send[1];
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14 : SDO <= to_send[0];
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endcase
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end
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end
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else if (active16) begin
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SCK <= ~SCK;
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if ( is16 == 31) begin
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active16 <= 0;
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SDO <= to_send[0];
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end
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else begin
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is16 <= is16 + 1;
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SDO <= SDO;
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case (is16)
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2 : SDO <= to_send[14];
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4 : SDO <= to_send[13];
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6 : SDO <= to_send[12];
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8 : SDO <= to_send[11];
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10 : SDO <= to_send[10];
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12 : SDO <= to_send[9];
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14 : SDO <= to_send[8];
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16 : SDO <= to_send[7];
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18 : SDO <= to_send[6];
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20 : SDO <= to_send[5];
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22 : SDO <= to_send[4];
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24 : SDO <= to_send[3];
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26 : SDO <= to_send[2];
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28 : SDO <= to_send[1];
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30 : SDO <= to_send[0];
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endcase
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end
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end
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end
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endmodule
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