21 lines
453 B
Verilog
21 lines
453 B
Verilog
/**
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* Tristate Buffer (16 bit)
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*
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* if (dir == 0) IN: PIN are set to High-Z, dataR = external PIN
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* if (dir == 1) OUTPUT: dataW is output to external PIN, dataR = dataW
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*/
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`default_nettype none
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module InOut(
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inout [15:0] PIN,
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input [15:0] dataW,
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output [15:0] dataR,
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input dir
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);
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// No need to implement this chip.
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// This chip is implemented using tristate value z
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assign PIN = dir? dataW: 16'bzzzzzzzzzzzzzzzz;
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assign dataR = PIN;
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endmodule
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