147 lines
4.5 KiB
Verilog
147 lines
4.5 KiB
Verilog
/**
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* The HACK computer, including CPU, ROM and RAM.
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* When RST is 1, the program stored in the computer's ROM executes.
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* When RST is 0, the execution of the program restarts.
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* Thus, to start a program's execution, reset must be pushed "down" (0)
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* and "up" (1). From this point onward the user is at the mercy of
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* the software. In particular, depending on the program's code, the
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* LED may show some output and the user may be able to interact
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* with the computer via the BUT.
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*/
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`default_nettype none
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module HACK(
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input CLK, // external clock 100 MHz
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input [1:0] BUT, // user button ("pushed down" == 0) ("up" == 1)
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output [1:0] LED, // leds (0 off, 1 on)
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input UART_RX, // UART recieve
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output UART_TX, // UART transmit
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output SPI_SDO, // SPI data out
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input SPI_SDI, // SPI data in
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output SPI_SCK, // SPI serial clock
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output SPI_CSX, // SPI chip select not
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output [17:0] SRAM_ADDR,// SRAM address 18 Bit = 256K
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inout [15:0] SRAM_DATA, // SRAM data 16 Bit
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output SRAM_WEX, // SRAM write_enable_not
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output SRAM_OEX, // SRAM output_enable_not
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output SRAM_CSX, // SRAM chip_select_not
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output LCD_DCX, // LCD data/command not
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output LCD_SDO, // LCD data out
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output LCD_SCK, // LCD serial clock
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output LCD_CSX, // LCD chip select not
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input RTP_SDI, // RTP data in s
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output RTP_SDO, // RTP data out
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output RTP_SCK // RTP serial clock
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);
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// Put your code here:
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wire loadRAM;
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wire loadIO0;
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wire loadIO1;
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wire loadIO2;
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wire loadIO3;
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wire loadIO4;
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wire loadIO5;
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wire loadIO6;
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wire loadIO7;
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wire loadIO8;
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wire loadIO9;
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wire loadIOA;
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wire loadIOB;
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wire loadIOC;
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wire loadIOD;
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wire loadIOE;
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wire loadIOF;
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wire [15:0] inRAM;
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wire [15:0] inIO0;
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wire [15:0] inIO1;
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wire [15:0] inIO2;
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wire [15:0] inIO3;
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wire [15:0] inIO4;
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wire [15:0] inIO5;
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wire [15:0] inIO6;
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wire [15:0] inIO7;
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wire [15:0] inIO8=0;
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wire [15:0] inIO9=0;
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wire [15:0] inIOA=0;
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wire [15:0] inIOB=0;
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wire [15:0] inIOC=0;
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wire [15:0] inIOD=0;
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wire [15:0] inIOE=0;
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wire [15:0] inIOF=0;
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wire writeM;
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wire [15:0] inM;
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wire [15:0] instruction;
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wire [15:0] outM;
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wire [15:0] addressM;
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wire [15:0] pc;
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wire clk, reset;
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wire [15:0] ROM_DATA;
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wire [15:0] fromLCD;
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//wire [15:0] outDEBUG0;
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//wire [15:0] outDEBUG1;
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//wire [15:0] outDEBUG2;
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//wire loadDEBUG0;
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//wire loadDEBUG1;
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//wire loadDEBUG2;
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// Put your code here:
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//assign SRAM_ADDR[17:16]=2'b0;
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assign LED[1:0] = inIO0[1:0];
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assign inIO8 = fromLCD;
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assign inIO9 = fromLCD;
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//assign outDEBUG0 = inIOB;
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//assign outDEBUG1 = inIOC;
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//assign outDEBUG2 = inIOD;
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//assign loadDEBUG0 = loadIOB;
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//assign loadDEBUG1 = loadIOC;
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//assign loadDEBUG2 = loadIOD;
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Clock25_Reset20 CLKR(CLK, clk, reset);
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CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc);
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Memory Memory(addressM, writeM, inM, loadRAM,
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loadIO0, loadIO1, loadIO2, loadIO3, loadIO4, loadIO5, loadIO6, loadIO7,
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loadIO8, loadIO9, loadIOA, loadIOB, loadIOC, loadIOD, loadIOE, loadIOF,
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inRAM, inIO0, inIO1, inIO2, inIO3, inIO4, inIO5, inIO6, inIO7,
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inIO8, inIO9, inIOA, inIOB, inIOC, inIOD, inIOE, inIOF);
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ROM ROM(pc, instruction);
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RAM3840 RAM(clk, addressM[11:0], outM, loadRAM, inRAM);
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Register LED12(clk, outM, loadIO0, inIO0);
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Register BUT12(clk, {14'b0, BUT[1:0]}, 1'b1, inIO1);
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UartTX UartTX(clk, loadIO2, outM, UART_TX, inIO2);
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UartRX UartRX(clk, loadIO3, UART_RX, inIO3);
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SPI SPI(clk, loadIO4, outM, inIO4, SPI_CSX, SPI_SDO, SPI_SDI, SPI_SCK);
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//GO GO(clk, loadIO5, pc, inIO6, SRAM_ADDR[15:0], inIO7, ROM_DATA, instruction);
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//Register SRAM_A(clk, outM, loadIO0, inIO6);
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//SRAM_D SRAM_D(clk, loadIO7, outM, inIO7, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX);
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//LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK);
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//Register DEBUG0(clk, outM, loadIOB, inIOB);
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//Register DEBUG1(clk, outM, loadIOC, inIOC);
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//Register DEBUG2(clk, outM, loadIOD, inIOD);
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//Register DEBUG3(clk, outM, loadIOE, inIOE);
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//Register DEBUG4(clk, outM, loadIOF, inIOF);
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//assign SPI_SDO=0;
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//assign SPI_SCK=0;
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//assign SPI_CSX=0;
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assign SRAM_DATA=0;
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assign SRAM_WEX=0;
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assign SRAM_OEX=0;
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assign SRAM_CSX=0;
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assign LCD_DCX=0;
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assign LCD_SDO=0;
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assign LCD_SCK=0;
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assign LCD_CSX=0;
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assign RTP_SDO=0;
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assign RTP_SCK=0;
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endmodule
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