27 lines
506 B
Verilog
27 lines
506 B
Verilog
/**
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* instruction memory at boot time
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* The instruction memory is read only (ROM) and
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* preloaded with 256 x 16bit of Hackcode holding the bootloader.
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*
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* instruction = ROM[pc]
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*/
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`default_nettype none
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module ROM(
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input [15:0] pc,
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output [15:0] instruction
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);
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// No need to implement this chip
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// The file ROM.BIN holds the hack code
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parameter ROMFILE = "ROM.hack";
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reg [15:0] mem [0:255];
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assign instruction = mem[pc[7:0]];
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initial begin
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$readmemb(ROMFILE,mem);
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end
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endmodule
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